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[AK4390]
AK4390
Ultra Low Latency 32-Bit DAC
GENERAL DESCRIPTION The AK4390 is a high performance stereo DAC capable of sampling up to 216kHz including a 32-bit digital filter. The modulator uses AKM's multi-bit architecture, delivering wide dynamic range while preserving linearity for improved THD+N performance. The AK4390 has fully differential switched-cap filter outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4390 accepts 192kHz PCM data, ideal for a wide range of applications including DVD-Audio, high end sound cards, digital audio Firewire and USB interface boxes, and digital mixers. FEATURES * 128-times Oversampling * Sampling Rate: 30kHz 216kHz * 32Bit 8x Digital Filter Ripple: 0.005dB, Attenuation: 100dB Low latency option: 7/fs * High Tolerance to Clock Jitter * Low Distortion Differential Output * Digital De-emphasis for 32, 44.1, 48kHz sampling * Soft Mute * Digital Attenuator (255 levels and 0.5dB step) * THD+N: -103dB * DR, S/N: 120dB * Audio Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S * Master Clock: 30kHz ~ 32kHz: 1152fs 30kHz ~ 54kHz: 512fs or 768fs 30kHz ~ 108kHz: 256fs or 384fs 108kHz ~ 216kHz: 128fs or 192fs * Power Supply: 5V 5% * TTL Level Digital I/F * Package: 30pin VSOP
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[AK4390]
Block Diagram
DVDD VSS3 PDN AVDD VSS4 VSS2 VDDL PCM Data Interface 8X Interpolator SCF AOUTLP AOUTLN
BICK LRCK SDATA
VREFHL DATT Soft Mute MCLK Clock Divider Modulator Vref VREFLL VREFLR VREFLL
AOUTRP CSN/SMUTE CCLK/DEM0 CDTI/DEM1 Control Register SCF AOUTRN VDDR VSS1 CAD0 CAD1/DIF0 PSN DZFL/DIF1 DIF2 DZFR
Block Diagram
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[AK4390]
Ordering Guide
AK4390EF AKD4390 -10 +70C 30pin VSOP (0.65mm pitch) Evaluation Board for AK4390
Pin Layout
SMUTE/CSN TST1/CAD0 DEM0/CCLK DEM1/CDTI DIF0/CAD1 DIF1/DZFL DIF2 PSN TST2/DZFR AOUTRP AOUTRN VSS1 VDDR VREFHR VREFLR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26
LRCK SDATA BICK PDN DVDD VSS4 MCLK AVDD VSS3 AOUTLP AOUTLN VSS2 VDDL VREFHL VREFLL
AK4390 Top View
25 24 23 22 21 20 19 18 17 16
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PIN/FUNCTION
No. Pin Name SMUTE CSN TST1 CAD0 DEM0 CCLK DEM1 CDTI DIF0 CAD1 DIF1 DZFL DIF2 PSN TST2 DZFR AOUTRP AOUTRN VSS1 VDDR VREFHR VREFLR VREFLL VREFHL VDDL VSS2 AOUTLN AOUTLP VSS3 AVDD MCLK VSS4 DVDD I/O I I I I I I I I I I I O I I I O O O I I I I O O I Function Soft Mute in Parallel Control Mode When this pin goes to "H", soft mute cycle is initiated. When returning to "L", the output mute releases. Chip Select in Serial Control Mode Test Pin in Parallel Control Mode (Internal pull-down pin) Chip Address 0 in Serial Control Mode (Internal pull-down pin) De-emphasis Enable 0 in Parallel Control Mode Control Data Clock in Serial Control Mode De-emphasis Enable 1 in Parallel Control Mode Control Data Input in Serial Control Mode Digital Input Format 0 in PCM Mode Chip Address 1 in Serial Control Mode Digital Input Format 1 in PCM Mode Left Channel Zero Input Detect in Serial Control Mode Digital Input Format 2 in PCM Mode Parallel/Serial Select (Internal pull-up pin) "L": Serial Control Mode, "H": Parallel Control Mode Test pin in Parallel Control Mode. Connect to GND. Rch Zero Input Detect in Serial Control Mode Right Channel Positive Analog Output Right Channel Negative Analog Output Connected to VSS2/3/4 Ground Right Channel Analog Power Supply, 4.75~5.25V Right Channel High Level Voltage Reference Input Right Channel Low Level Voltage Reference Input Left Channel Low Level Voltage Reference Input Left Channel High Level Voltage Reference Input Left Channel Analog Power Supply, 4.75~5.25V Ground (connected to VSS1/3/4 ground) Left Channel Negative Analog Output Left Channel Positive Analog Output Ground (connected to VSS1/2/4 ground) Analog Power Supply, 4.75 to 5.25V
1
2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Master Clock Input Connected to VSS1/2/3 Ground Digital Power Supply, 4.75 5.25V Power-Down Mode 27 PDN I When at "L", the AK4390 is in power-down mode and is held in reset. The AK4390 should always be reset upon power-up. 28 BICK I Audio Serial Data Clock in PCM Mode 29 SDATA I Audio Serial Data Input in PCM Mode 30 LRCK I L/R Clock in PCM Mode Note: All input pins except internal pull-up/down pins should not be left floating.
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Handling of Unused Pin
The following tables illustrate recommended states for open pins: (1) Parallel Control Mode Classification Analog Digital (2) Serial Control Mode Pin Name Setting Leave open.
AOUTLP, AOUTLN AOUTRP, AOUTRN Leave open. SMUTE Connect to VSS4.
Classification Analog Digital
Pin Name AOUTLP, AOUTLN AOUTRP, AOUTRN DIF2 DZFL, DZFR
Setting Leave open. Leave open. Connect to VSS4. Leave open.
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[AK4390]
ABSOLUTE MAXIMUM RATINGS (VSS1 = VSS2 = VSS3 = VSS4 = 0V; Note 1) Parameter Symbol min Power Supplies: Analog AVDD -0.3 Analog VDDL/R -0.3 Digital DVDD -0.3 Input Current, Any pin Except Supplies IIN Digital Input Voltage VIND -0.3 Ambient Temperature (Power applied) Ta -10 Storage Temperature Tstg -65
Note 1. All voltages with respect to ground. Note 2. VSS1/2/3/4 must be connected to the same analog ground plane.
max 6.0 6.0 6.0 10 DVDD+0.3 70 150
Units V V V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (VSS1 = VSS2 = VSS3 = VSS4 =0V; Note 1) Parameter Symbol min typ Analog Power Supplies: AVDD 4.75 5.0 Analog (Note 3) VDDL/R 4.75 5.0 Digital DVDD 4.75 5.0 "H" voltage reference Voltage Reference VREFHL/R AVDD-0.5 "L" voltage reference (Note 4) VREFLL/R VSS3 VREFH-VREFL 3.0 VREF
Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not critical. Note 4. Analog output voltage scales with the voltage of (VREFH - VREFL). AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 2.8Vppx (VREFHL/R - VREFLL/R)/5.
max 5.25 5.25 5.25 AVDD AVDD
Units V V V V V V
* AKEMD assumes no responsibility for the usage beyond the conditions in this data sheet.
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ANALOG CHARACTERISTICS (Ta=25C; AVDD=VDDL/R=DVDD=5.0V; VSS1 = VSS2 = VSS3 = VSS4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS1=VSS2=VSS3; Input data=24bit; RL 1k; BICK=64fs; Input Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 15; unless otherwise specified.) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 5) 0dBFS -103 93 dB fs=44.1kHz THD+N BW=20kHz -57 dB -60dBFS 0dBFS -100 dB fs=96kHz BW=40kHz -54 dB -60dBFS 0dBFS -100 dB fs=192kHz BW=40kHz -60dBFS -54 dB BW=80kHz -51 dB -60dBFS Dynamic Range (-60dBFS with A-weighted) (Note 6) 114 120 dB S/N (A-weighted) (Note 7) 114 120 dB Interchannel Isolation (1kHz) 110 120 dB DC Accuracy Interchannel Gain Mismatch 0.15 0.3 dB Gain Drift (Note 8) 20 ppm/C Output Voltage (Note 9) 2.65 2.8 2.95 Vpp Load Capacitance 25 pF Load Resistance (Note 10) 1 k Power Supplies Power Supply Current Normal operation (PDN pin = "H") AVDD, VDDL/R 60 90 mA 43 mA DVDD (fs 96kHz) 46 70 mA DVDD (fs = 192kHz) Power down (PDN pin = "L") (Note 11) AVDD+DVDD 10 100 A
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual. Note 6. By Figure 15. External LPF Circuit Example 2.101dB for 16-bit data and 118dB for 20-bit data. Note 7. By Figure 15. External LPF Circuit Example 2. S/N does not depend on input word length. Note 8. The voltage on (VREFHL/R - VREFLL/R) is held +5V externally. Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R - VREFLL/R). AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 2.8Vpp x (VREFHL/R - VREFLL/R)/5. Note 10. For AC-load. 1.5k for DC-Load Note 11. In the power-down mode. PSN pin = DVDD, and all other digital input pins including clock pins (MCLK, BICK and LRCK) are held VSS4. Note 12. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. The VREFHL/R pin is held +5V.
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SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V; Normal Speed Mode; DEM=OFF; SD bit ="0") Parameter Symbol min typ max Units Digital Filter Passband (Note 14) 0.01dB PB 0 20.0 kHz -6.0dB 22.05 kHz Stopband (Note 13) SB 24.1 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 100 dB Group Delay (Note 14) GD 36 1/fs Digital Filter + SCF Frequency Response : 0 20.0kHz 0.2 dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Double Speed Mode; DEM=OFF; SD bit="0") Parameter Symbol min typ max Units Digital Filter Passband (Note 13) 0.01dB PB 0 43.5 kHz -6.0dB 48.0 kHz Stopband (Note 13) SB 52.5 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 95 dB Group Delay (Note 14) GD 36 1/fs Digital Filter + SCF Frequency Response : 0 40.0kHz 0.3 dB
SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Quad Speed Mode; DEM=OFF; SD bit="0") Parameter Symbol min typ max Units Digital Filter Passband (Note 13) 0.01dB PB 0 87.0 kHz -6.0dB 96.0 kHz Stopband (Note 13) SB 105 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 90 dB Group Delay (Note 14) GD 36 1/fs Digital Filter + SCF Frequency Response : 0 80.0kHz +0/-1 dB
Note 13. The passband and stopband frequencies scale with fs. For example, PB=0.4535xfs (@0.01dB), SB=0.546xfs. Note 14. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal.
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Short Delay FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Normal Speed Mode; DEM=OFF; SD bit="1") Parameter Symbol min typ max Units Digital Filter Passband (Note 14) 0.01dB PB 0 20.0 kHz -6.0dB 22.05 kHz Stopband (Note 13) SB 24.1 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 100 dB Group Delay (Note 14) GD 7 1/fs Digital Filter + SCF Frequency Response : 0 20.0kHz 0.2 dB
Short Delay FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Double Speed Mode; DEM=OFF; SD bit="1") Parameter Symbol min typ max Units Digital Filter Passband (Note 13) 0.01dB PB 0 43.5 kHz -6.0dB 48.0 kHz Stopband (Note 13) SB 52.5 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 95 dB Group Delay (Note 14) GD 7 1/fs Digital Filter + SCF Frequency Response : 0 40.0kHz 0.3 dB
Short Delay FILTER CHARACTERISTICS (fs = 192kHz) (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Quad Speed Mode; DEM=OFF; SD bit="1") Parameter Symbol min typ max Units Digital Filter Passband (Note 13) 0.01dB PB 0 87.0 kHz -6.0dB 96.0 kHz Stopband (Note 13) SB 105 kHz Passband Ripple PR 0.005 dB Stopband Attenuation SA 90 dB Group Delay (Note 14) GD 7 1/fs Digital Filter + SCF Frequency Response : 0 80.0kHz +0/-1 dB
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DC CHARACTERISTICS (Ta=25C; AVDD=VDDL/R=4.75 ~ 5.25V, DVDD=4.75 ~ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.4 Low-Level Input Voltage VIL High-Level Output Voltage (Iout = -100A) VOH DVDD-0.5 Low-Level Output Voltage (Iout = 100A) VOL Input Leakage Current (Note 15) Iin -
typ -
max 0.8 0.5 10
Units V V V V A
Note 15. TST1/CAD0 and PSN pins have internal pull-up devices, nominally 100k. Therefore, TST1/CAD0 and PSN pins are not included in this specification.
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[AK4390]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V) Parameter Symbol min Master Clock Timing Frequency fCLK 7.7 Duty Cycle dCLK 40 LRCK Frequency (Note 16) Normal Speed Mode fsn 30 Double Speed Mode fsd 30 Quad Speed Mode fsq 108 Duty Cycle Duty 45 PCM Audio Interface Timing BICK Period 1/128fn tBCK Normal Speed Mode 1/64fd tBCK Double Speed Mode 1/64fq tBCK Quad Speed Mode 30 tBCKL BICK Pulse Width Low 30 tBCKH BICK Pulse Width High 20 tBLR BICK "" to LRCK Edge (Note 17) 20 tLRB LRCK Edge to BICK "" (Note 17) 20 tSDH SDATA Hold Time 20 tSDS SDATA Setup Time Control Interface Timing 200 tCCK CCLK Period 80 tCCKL CCLK Pulse Width Low 80 tCCKH Pulse Width High 50 tCDS CDTI Setup Time 50 tCDH CDTI Hold Time 150 tCSW CSN High Time 50 tCSS CSN "" to CCLK "" 50 tCSH CCLK "" to CSN "" Reset Timing PDN Pulse Width (Note 18) tPD 150
typ
max 41.472 60 54 108 216 55
Units MHz % kHz kHz kHz %
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 16. When the frequency (1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs) is switched, the AK4390 should be reset by the PDN pin or RSTN bit. Note 17. BICK rising edge must not occur at the same time as LRCK edge. Note 18. The AK4390 can be reset by bringing the PDN pin "L" to "H".
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[AK4390]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDATA
VIH VIL
Audio Interface Timing (PCM Mode)
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[AK4390]
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
WRITE Command Input Timing
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
WRITE Data Input Timing
tPD PDN VIL
Power Down & Reset Timing
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[AK4390]
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4390, are MCLK, BICK and LRCK. MCLK should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the initial master clock is set to the appropriate frequency (Table 1). When external clocks are changed, the AK4390 should be reset by the PDN pin or RSTN bit. After exiting reset (PDN pin = "L" "H") at power-up etc., the AK4390 is in power-down mode until MCLK is supplied. The AK4390 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode, and the analog output is AVDD/2 (typ). When MCLK and LRCK are input again, the AK4390 is powered up. After power-up, the AK4390 is in the power-down mode until MCLK and LRCK are input. The MCLK frequency corresponding to each sampling speed should be provided (Table 2). MCLK 1152fs 512fs 256fs 128fs Mode Normal 768fs Normal 384fs Double 192fs Quad Table 1. Sampling Speed Sampling Rate 30kHz~32kHz 30kHz~54kHz 30kHz~108kHz 108kHz~216kHz
LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs N/A N/A N/A N/A N/A 22.5792 24.5760
MCLK (MHz) 192fs 256fs 384fs 512fs N/A 8.1920 12.2880 16.3840 N/A 11.2896 16.9344 22.5792 N/A 12.2880 18.4320 24.5760 N/A 22.5792 33.8688 N/A N/A 24.5760 36.8640 N/A 33.8688 N/A N/A N/A 36.8640 N/A N/A N/A Table 2. System Clock Example (N/A: Not available)
768fs 24.5760 33.8688 36.8640 N/A N/A N/A N/A
1152fs 36.8640 N/A N/A N/A N/A N/A N/A
MCLK= 256fs/384fs supports sampling rate of 30kHz~108kHz (Table 3). But, when the sampling rate is 30kHz~54kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. MCLK DR,S/N 256fs/384fs 117dB 512fs/768fs 120dB Table 3. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
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[AK4390]
Audio Interface Format
Data is shifted in via the SDATA pin using the BICK and LRCK inputs. Eight data formats are supported, selected by the DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 4. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and 16-bit MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 5 6 7 DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 Input Format BICK 0 16bit LSB justified 32fs 1 20bit LSB justified 48fs 0 24bit MSB justified 48fs 1 24bit I2S Compatible 48fs 0 24bit LSB justified 48fs 1 32bit LSB justified 64fs 0 32bit MSB justified 64fs 1 32bit I2S Compatible 64fs Table 4. Audio Interface Format Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Figure 5 Figure 5 Figure 6
(default)
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK (32fs) SDATA Mode 0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
0
15
1
14
6
14
5
15
4
16
3
17
2
1
31
0
15
0
14
1
BICK (64fs) SDATA Mode 0
Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0
Lch Data
Figure 1. Mode 0 Timing
Rch Data
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK (64fs) SDATA Mode 1 SDATA Mode 4
Don't care 19:MSB, 0:LSB Don't care 23 22 21 20 19 0 Don't care 23 22 21 20 19 0 19 0 Don't care 19 0
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1/4 Timing
Rch Data
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[AK4390]
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDATA
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23 22
Lch Data
Figure 3. Mode 2 Timing
Rch Data
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK (64fs) SDATA
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDATA
32 31 32:MSB, 0:LSB 1 0 32 31 1 0 32 31
Lch Data
Figure 5. Mode 5/6 Timing
Rch Data
LRCK
0 1 2 3 30 31 32 0 1 2 3 30 31 32 0 1
BICK (64fs) SDATA
31 30 31:MSB, 0:LSB 1 0 Don't care 31 30 1 0 Don't care 31
Lch Data
Figure 6. Mode 7 Timing
Rch Data
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De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15s) and it is enabled or disabled with the DEM1-0 pins or DEM1-0 bits. For 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is always off. When in DSD mode, the DEM1-0 bits are ignored. The current value is held even if PCM mode and DSD mode are switched. DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF (default) 0 48kHz 1 32kHz Table 5. De-emphasis Control
Output Volume Control
The AK4390 includes channel independent digital output volume control (ATT) with 256 levels at 0.5dB steps including MUTE. The volume control is in front of the DAC, and it can attenuate the input data from 0dB to -127dB and mute. When changing output levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions.
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Zero Detection
The AK4390 has a channel-independent zero detect function. When the input data for each channel is continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes to "H". The DZF pin of each channel immediately returns to "L" if the input data of either channel is not zero after going to "H". If the RSTN bit is "0", the DZF pins for both channels go to "H". The DZF pins of both channels go to "L" 4 ~ 5/fs after the RSTN bit returns to "1". If the DZFM bit is set to "1", the DZF pins of both channels go to "H" only when the input data for both channels are continuously zero for 8192 LRCK cycles. The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels are always "L". The DZFB bit can invert the polarity of the DZF pin.
Soft Mute Operation
The soft mute operation is performed in the digital domain. When the SMUTE pin changes to "H" or the SMUTE bit set to "1", the output signal is attenuated by - during ATT_DATA x ATT transition time from the current ATT level. When the SMUTE pin is returned to "L" or the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA x ATT transition time. If the soft mute is cancelled before attenuating - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
S M U T E pin or S M U T E bit (1) AT T _Level A ttenuation (3) (1)
-
GD (2) AOUT (4) 8192/fs GD (2)
D ZF pin
Notes: (1) ATT_DATA x ATT transition time (Table 9). For this example, the time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in Normal Speed Mode. (2) Analog output corresponding to digital input has group delay (GD). (3) If the soft mute is cancelled before attenuating - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data for each channel is continuously zero for 8192 LRCK cycles, the DZF pin for each channel goes to "H". The DZF pin immediately returns to "L" if the input data are not zero after going "H". Figure 7. Soft Mute Function
System Reset
The AK4390 should be reset once by bringing the PDN pin = "L" upon power-up. The analog section exits power-down mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs.
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[AK4390]
Power ON/OFF timing
The AK4390 is placed in the power-down mode by bringing the PDN pin "L" and the registers are initialized. the analog outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be muted externally if the click noise influences system application. The DAC can be reset by setting RSTN bit to "0". In this case, the registers are not initialized and the corresponding analog outputs go to AVDD/2 (typ). As some click noise occurs at the edge of RSTN signal, the analog output should be muted externally if click noise aversely affect system performance.
Power PDN pin
(1)
Internal State
Normal Operation
Reset
DAC In (Digital)
"0"data GD (2)
"0"data GD (4) (3)
DAC Out (Analog) Clock In
MCLK,LRCK,BICK
(3)
(4)
(5)
Don't care
Don't care
DZFL/DZFR
(7)
External Mute
(6)
Mute ON
Mute ON
Notes: (1) After AVDD and DVDD are powered-up, the PDN pin should be "L" for 150ns. (2) The analog output corresponding to digital input has group delay (GD). (3) Analog outputs are floating (Hi-Z) in power-down mode. (4) Click noise occurs at the edge of PDN signal. This noise is output even if "0" data is input. (5) Mute the analog output externally if click noise (3) adversely affect system performance The timing example is shown in this figure. (6) DZFL/R pins are "L" in the power-down mode (PDN pin = "L"). (DZFB bit = "0") Figure 8. Power-down/up Sequence Example
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[AK4390]
Reset Function
(1) RESET by RSTN bit = "0" When the RSTN bit = "0", the AK4390's digital section is powered down, but the internal register values are not initialized. The analog outputs settle to AVDD/2 (typ) and the DZF pins for both channels go to "H". Figure 9 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (5) 2~3/fs (5)
Internal RSTN bit Internal State D/A In (Digital) (1) D/A Out (Analog) DZF
GD
Normal Operation
D igital Block P d
Normal O peration
"0 " data GD
(3)
(2)
(3)
(1)
2/ fs(4)
(6)
Notes: (1) The analog output corresponding to digital input has group delay (GD). (2) Analog outputs settle to AVDD/2 (typ). (3) Click noise occurs at the edges (" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) DZF pins go to "H" when the RSTN bit is set to "0", and return to "L" at 2/fs after the RSTN bit becomes "1". (5) There is a delay, 3 ~ 4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2 ~ 3/fs from RSTN bit "1" to the internal RSTN bit "1". (6) Mute the analog output externally if click noise (3) adversely affect system performance Figure 9. Reset Sequence Example 1
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[AK4390]
(2) RESET by MCLK or LRCK stop The AK4390 is automatically placed in reset state when MCLK or LRCK is stopped during normal operation and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4390 exits reset state and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped.
AVDD pin DVDD pin RSTB pin
Internal State D/A In (Digital) (1)
Power-down
Normal O peration
Digital Circuit P ower-down
Normal Operation
Power-down GD
(3) (2) (4) (4) (5)
MCLK, BICK, LRCK Stop
(5) GD
(2)
D/A Out (Analog)
Clock In
MCLK, BICK, LRCK
Hi-Z
(4)
External MUTE
(6)
(6)
(6)
Notes: (1) After AVDD and DVDD are powered-up, the PDN pin should be held "L" for 150ns. (2) The analog output corresponding to digital input has the group delay (GD). (3) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting the "0" data during this period. (4) Click noise occurs in 3 4LRCK cycles ether on a rising edge () of the PDN signal or MCLK inputs. This noise is output even if "0" data is input. (5) Mute the analog output externally if click noise (4) influences system application. The timing example is shown in this figure. Figure 10. Reset Sequence Example 2
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[AK4390]
Register Control Interface
Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4390. In parallel control mode, the register setting is ignored, and in serial control mode the pin settings are ignored. When the state of the PSN pin is changed, the AK4390 should be reset by the PDN pin. The serial control interface is enabled by the PSN pin = "L". In this mode, pin settings must be all "L". Internal registers may be written to through3-wire P interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, CAD0/1), Read/Write (1-bit; fixed to "1"), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The AK4390 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The writing of data is valid when CSN "". The clock speed of CCLK is 5MHz (max). Function Parallel Control Mode Serial Control Mode Audio Format Y Y De-emphasis Y Y SMUTE Y Y DSD Mode Y EX DF I/F Y Short delay Filter Y Digital Attenuator Y Table 6. Function List (Y: Available, -: Not available) Setting the PDN pin to "L" resets the registers to their default values. In serial control mode, the internal timing circuit is reset by the RSTN bit, but the registers are not initialized.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: READ/WRITE (Fixed to "1", Write only) A4-A0: Register Address D7-D0: Control Data Figure 11. Control I/F Timing
* The AK4390 does not support the read command. * When the AK4390 is in power down mode (PDN pin = "L") or the MCLK is not provided, writing into the control register is prohibited. * The control data can not be written when the CCLK rising edge is 15 times or less or 17 times or more during CSN is "L".
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Function List Function Attenuation Level Default 0dB Address 03H 04H 00H 00H 00H 01H 01H 01H 01H 01H 02H 02H Bit ATT7-0 PCM Y Y Y Y Y Y Y Y Y Y Y Y DSD Y Y Y Y Y Y Y Y Y Ex DF I/F Y Y Y Y Y Y
External Digital Filter I/F Mode Disable EXDF Ex DF I/F mode clock setting 16fs(fs=44.1kHz) ESC Audio Data Interface Modes 24bit MSB justified DIF2-0 Data Zero Detect Enable Disable DZFE Data Zero Detect Mode Separated DZFM Short delay Filter Enable Sharp roll-off filter SD De-emphasis Response OFF DEM1-0 Soft Mute Enable Normal Operation SMUTE DSD/PCM Mode Select PCM mode DP Master Clock Frequency Select at 512fs DCKS DSD mode MONO mode Stereo mode select Stereo 02H MONO Inverting Enable of DZF "H" active 02H DZFB The data selection of L channel and R channel 02H SELLR R channel Table 7. Function List2 (Y: Available, -: Not available)
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[AK4390]
Register Map
Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 0 DZFE 0 ATT7 ATT7 D6 0 DZFM 0 ATT6 ATT6 D5 0 SD 0 ATT5 ATT5 D4 0 DFS1 0 ATT4 ATT4 D3 DIF2 DFS0 0 ATT3 ATT3 D2 DIF1 DEM1 DZFB ATT2 ATT2 D1 DIF0 DEM0 0 ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0
Notes: Data must not be written into addresses from 05H to 1FH. When the PDN pin goes to "L", the registers are initialized to their default values. When RSTN bit is set to "0", only the internal timing is reset, and the registers are not initialized to their default values. When the state of the PSN pin is changed, the AK4390 should be reset by the PDN pin.
Register Definitions
Addr Register Name 00H Control 1 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 DIF2 0 D2 DIF1 1 D1 DIF0 0 D0 RSTN 1
RSTN: Internal timing reset 0: Reset. All registers are not initialized. 1: Normal Operation (default) When internal clocks are changed, the AK4390 should be reset by the PDN pin or RSTN bit. DIF2-0: Audio data interface modes (Table 4) Initial value is "010" (Mode 2: 24-bit MSB justified).
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[AK4390]
Addr Register Name 01H Control 2 Default
D7 DZFE 0
D6 DZFM 0
D5 SD 0
D4 0 0
D3 0 0
D2 DEM1 0
D1 DEM0 1
D0 SMUTE 0
SMUTE: Soft Mute Enable 0: Normal Operation (default) 1: DAC outputs soft-muted. DEM1-0: De-emphasis Response (Table 5) Initial value is "01" (OFF). SD: Short Delay Filter Enable 0: Sharp roll-off filter (default) 1: Short Delay filter Data Zero Detect Mode 0: Channel Separated Mode (default) 1: Channel AND'ed Mode If the DZFM bit is set to "1", the DZF pins of both channels goes to "H" only when the input data for both channels are continuously zero for 8192 LRCK cycles. Data Zero Detect Enable 0: Disable (default) 1: Enable The zero detect function can be disabled by DZFE bit "0". In this case, the DZF pins of both channels are always "L".
DZFM:
DZFE:
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[AK4390]
Addr Register Name 02H Control 3 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 DZFB 0
D1 0 0
D0 0 0
DZFB: Inverting Enable of DZF 0: DZF pin goes "H" at Zero Detection (default) 1: DZF pin goes "L" at Zero Detection
Addr Register Name 03H Lch ATT 04H Rch ATT Default
D7 ATT7 ATT7 1
D6 ATT6 ATT6 1
D5 ATT5 ATT5 1
D4 ATT4 ATT4 1
D3 ATT3 ATT3 1
D2 ATT2 ATT2 1
D1 ATT1 ATT1 1
D0 ATT0 ATT0 1
ATT7-0: Attenuation Level 256 levels, 0.5dB step Data FFH FEH FDH : : 02H 01H 00H Attenuation 0dB -0.5dB -1.0dB : : -126.5dB -127.0dB MUTE (-)
The transition between set values is a soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from FFH (0dB) to 00H (MUTE). If the PDN pin goes to "L", the ATTs are initialized to FFH. The ATT values are FFH when RSTN = "0". When RSTN return to "1", the ATT values fade to their current value. This digital attenuator is independent of the soft mute function.
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[AK4390]
SYSTEM DESIGN
Figure 12 shows the system connection diagram. Figure 14 and Figure 15 shows the analog output circuit examples. The evaluation board (AKD4390) demonstrates the optimum layout, power supply arrangements and measurement results.
Digital 5.0V
1 2
CSN CAD0 CCLK CDTI CAD1 DZFL DIF2 PSN DZFR AOUTRP AOUTRN VSS1 VDDR VREFHR VREFLR AK4390 Top View
LRCK SDATA
30 29
MicroController
3 4 5 6 7 8 9 BICK 28
DSP
PDN 27 DVDD VSS4 MCLK AVDD 26 25 24 23 0.1u + 10u 0.1u + 10u
VSS3 22 AOUTLP 21 AOUTLN 20 VSS2 19 VDDL 18 VREFHL 17 VREFLL 16
Rch Out
Rch Mute
Rch LPF
10 11 12
Lch LPF
Lch Mute
Lch Out
10u + + 10u
0.1u
13 14
0.1u
10u + + 10u
0.1u
15
0.1u
Digital Ground
Analog Ground
Analog 5.0V
+
Electrolytic Capacitor Ceramic Capacitor
Notes: - Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. - VSS1/2/3/4 must be connected to the same analog ground plane. - When AOUT drives a capacitive load, some resistance should be added in series between AOUT and the capacitive load. - All input pins except pull-down/pull-up pins should not be allowed to float. Figure 12. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial Control Mode)
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[AK4390]
Digital Ground
Analog Ground
1 2 3 4 SMUTE/CSN TST1/CAD0 DEM0/CCLK DEM1/CDTI DIF0/CAD1 DIF1/DZFL DIF2 PSN TST2/DZFR AOUTRP AOUTRN VSS1 VDRR VREFHR VREFLR LRCK SDATA BICK PDN DVDD VSS4 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
System Controller
5 6 7 8 9 10 11 12 13 14 15
AK4390
MCLK AVDD VSS3 AOUTLP AOUTLN VSS2 VDDL VREFHL VREFLL
Figure 13. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively. AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. The power up sequence between AVDD and DVDD is not critical. VSS1/2/3/4 must be connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R should be connected with a 0.1F ceramic capacitor. All signals, especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4390.
3. Analog Outputs
The analog outputs are fully differential outputs at 2.8Vpp (typ, VREFHL/R - VREFLL/R = 5V), centered around AVDD/2 (typ). The differential outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R - VREFLL/R = 5V). The bias voltage of the external summing circuit is supplied externally. The input data format is two's complement. The output voltage (VAOUT) is positive full scale for 7FFFFFH (@24-bits) and negative full scale for 800000H (@24-bits). The ideal VAOUT is 0V for 000000H(@24-bits). The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Figure 14 shows an example of an external LPF circuit summing the differential outputs with an op-amp. Figure 15 shows an example of differential outputs and a LPF circuit example by three op-amps.
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[AK4390]
AK4390
AOUT1.5k 750 2.2n 1.5k 1.5k 1.5k 1n
+Vop
AOUT+
750 1n
-Vop
Analog Out
Figure 14. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)
Frequency Response Gain 20kHz -0.012dB 40kHz -0.083dB 80kHz -0.799dB Table 8. Filter Response of External LPF Circuit Example 1 for PCM
3.3n
+
+15 -15
100u
AOUTL- +
10u
180 3.9n
10k
330
7 3 2+ 4
0.1u
6 +
NJM5534D
10u
560 1.0n 620 560 620
0.1u
10u +
680 1.2k
0.1u
3.3n
+
1.0n NJM5534D
2- 4 + 3 7
100
6
Lch
100u
AOUTL+ +
180 3.9n
10u 0.1u
+
10k
330
7 3 + 24
0.1u
6 +
10u
NJM5534D
10u
1.2k
680
0.1u
Figure 15. External LPF Circuit Example 2 for PCM 1st Stage 2nd Stage Total Cut-off Frequency 182kHz 284kHz Q 0.637 Gain +3.9dB -0.88dB +3.02dB 20kHz -0.025 -0.021 -0.046dB Frequency 40kHz -0.106 -0.085 -0.191dB Response 80kHz -0.517 -0.331 -0.848dB Table 9. Filter Response of External LPF Circuit Example 2 for PCM
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[AK4390]
PACKAGE
30pin VSOP (Unit: mm)
*9.70.1 0.3 30 1.5MAX
16 A 7.60.2 0.15 +0.10 -0.05 Detail A 0.450.2
1 0.220.1
15 0.65
0.12 M
1.20.10
0.08
NOTE: Dimension "*" does not include mold flash.
Material & Lead finish
Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
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0.10 -0.05
+0.10
5.60.1
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[AK4390]
MARKING
AK4390EF XXXXXXXXX
XXXXXXXXX
Date code identifier
REVISION HISTORY
Date (YY/MM/DD) 09/01/09 Revision 00 Reason First Edition Page Contents
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[AK4390]
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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